Verilog to SystemVerilog Cheat Sheet

Lesson B.4's Concept Review link opens a one-page mapping of every construct covered in Lessons B.1 through B.3: wire/reg to logic, always @(*) to always_comb, always @(posedge clk) to always_ff, and a short preview of assert property (...), interface, and enum.

Keep it open in a tab when you start Course 2's first testbench — it is a reference, not new material, so there is nothing further to learn here beyond what B.1 through B.3 already covered.